Arm CSSC quick reference

The AArch64 FEAT_CSSC (Common Short Sequence Compression) extension adds a few instructions operating on general purpose registers. The extension is optional since Armv8.7, and mandatory since Armv8.9 if FEAT_AdvSIMD is implemented. The most interesting addition is a popcnt instruction operating on general purpose registers, but the full list of new instructions is:

CSSC instruction	Equivalent pre-CSSC sequence (†)
`ABS Rd, Rn`	`TST Rn, Rn CNEG Rd, Rn, MI`
`CNT Rd, Rn`	`FMOV d0, Rn CNT v0.8B, v0.8B ADDV b0, v0.8B FMOV Rd, s0`
`CTZ Rd, Rn`	`RBIT Rd, Rn CLZ Rd, Rd`
`SMAX Rd, Rn, Rm`	`CMP Rn, Rm CSEL Rd, Rn, Rm, GT`
`SMAX Rd, Rn, #i8`	`MOV Rtmp, #i8 CMP Rn, Rtmp CSEL Rd, Rn, Rtmp, GT`
`SMIN Rd, Rn, Rm`	`CMP Rn, Rm CSEL Rd, Rn, Rm, LT`
`SMIN Rd, Rn, #i8`	`MOV Rtmp, #i8 CMP Rn, Rtmp CSEL Rd, Rn, Rtmp, LT`
`UMAX Rd, Rn, Rm`	`CMP Rn, Rm CSEL Rd, Rn, Rm, HI`
`UMAX Rd, Rn, #u8`	`MOV Rtmp, #u8 CMP Rn, Rtmp CSEL Rd, Rn, Rtmp, HI`
`UMIN Rd, Rn, Rm`	`CMP Rn, Rm CSEL Rd, Rn, Rm, LO`
`UMIN Rd, Rn, #u8`	`MOV Rtmp, #u8 CMP Rn, Rtmp CSEL Rd, Rn, Rtmp, LO`

(†) Except that the CSSC instructions do not mutate flags, and CSSC CNT does not mutate any SIMD registers.